UART-Sender (8N1)

module uart_tx(input CLK, RST, START, input [7:0] D, output TX, output BUSY);
  reg [9:0] sh;
  reg [3:0] n;
  reg s1;
  always @(posedge CLK or posedge RST)
    if (RST) begin sh <= 10'h3FF; n <= 4'd0; s1 <= 1'b0; end
    else begin
      s1 <= START;
      if (n == 0) begin
        if (START && !s1) begin sh <= {1'b1, D, 1'b0}; n <= 4'd10; end
      end else begin
        sh <= {1'b1, sh[9:1]};
        n <= n - 4'd1;
      end
    end
  assign TX = sh[0];
  assign BUSY = n != 0;
endmodule