Verilog (digital engine)v_uart_tx

UART transmitter (8N1)

Sends D on a rising START edge; one bit per clock (clock = baud rate)

Schematic symbol

Key data

Category: Logic (Verilog)
Simulation model: Verilog (digital engine)
Reference prefix: U
Pins: 15
Land pattern: SOIC-16_3.9mm_P1.27mm

Simulation model

The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.

Supply pins: VCC / GND
Output driver resistance: 50 Ω

Verilog source

module uart_tx(input CLK, RST, START, input [7:0] D, output TX, output BUSY);
  reg [9:0] sh;
  reg [3:0] n;
  reg s1;
  always @(posedge CLK or posedge RST)
    if (RST) begin sh <= 10'h3FF; n <= 4'd0; s1 <= 1'b0; end
    else begin
      s1 <= START;
      if (n == 0) begin
        if (START && !s1) begin sh <= {1'b1, D, 1'b0}; n <= 4'd10; end
      end else begin
        sh <= {1'b1, sh[9:1]};
        n <= n - 4'd1;
      end
    end
  assign TX = sh[0];
  assign BUSY = n != 0;
endmodule

Pins 15

Pin	Name	Use
CLK	CLKInput pin	Logic input: never leave open (tie unused inputs to VCC or GND)
RST	RSTInput pin	Logic input: never leave open (tie unused inputs to VCC or GND)
START	STARTInput pin	Logic input: never leave open (tie unused inputs to VCC or GND)
D[0]	D[0]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
D[1]	D[1]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
D[2]	D[2]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
D[3]	D[3]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
D[4]	D[4]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
D[5]	D[5]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
D[6]	D[6]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
D[7]	D[7]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
TX	TXOutput pin	Logic output: drives the next input; do not tie outputs together
BUSY	BUSYOutput pin	Logic output: drives the next input; do not tie outputs together
VCC	VCCSupply pin	Supply input: decouple with 100 nF close to the pin
GND	GNDGround pin	Ground

Parameters 1

Gate delaytpd

Default1n s

Delay per gate / clock→Q

PCB

Generic land patternSOIC-16_3.9mm_P1.27mm

no known land pattern, generic SOIC-16_3.9mm_P1.27mm with pins in symbol order