Behavioural mixed-signal modelLAN8720A-CPlan8720a
LAN8720A Ethernet PHY (RMII)
10/100 Ethernet transceiver with RMII to the MAC: TXD0/1, TXEN, RXD0/1, CRS_DV and the 50 MHz reference clock (REFCLKO with a 25 MHz crystal on XTAL1/2, or 50 MHz into CLKIN), management on MDC/MDIO (IEEE 802.3 clause 22, PHY address from the RXER/PHYAD0 strap, default 0). TXP/TXN/RXP/RXN to an RJ45 jack with magnetics; link when a cable is plugged into it. RBIAS 12.1 kΩ 1 % to GND. Supply 3.3 V (VDD1A, VDD2A, VDDIO), VDDCR from the internal regulator with 470 pF + 1 µF.
Key data
- Category
- Interfaces
- Simulation model
- Behavioural mixed-signal model
- Manufacturer part number
- LAN8720A-CP
- Reference prefix
- U
- Pins
- 25
- Land pattern
- VQFN-24-1EP_4x4mm_P0.5mm_EP2.5x2.5mm_ThermalVias
Simulation model
A behavioural model implements the interface of the chip (registers, protocol, timing) at its pins. The pins are connected to the analog circuit like CMOS pins.
- Model
- lan8720a
- Supply pins
- VDDIO / VSS
Pins 25
| Pin | Name | Use |
|---|---|---|
| XTAL2 | XTAL2Analog pin | General-purpose I/O: LEDs (with series resistor), buttons (with pull-up) |
| XTAL1 | XTAL1/CLKINAnalog pin | General-purpose I/O: LEDs (with series resistor), buttons (with pull-up) |
| RXD1 | RXD1/MODE1Output pin | Logic output: drives the next input; do not tie outputs together |
| RXD0 | RXD0/MODE0Output pin | Logic output: drives the next input; do not tie outputs together |
| RXER | RXER/PHYAD0Output pin | Logic output: drives the next input; do not tie outputs together |
| CRS_DV | CRS_DV/MODE2Output pin | Logic output: drives the next input; do not tie outputs together |
| MDIO | MDIOI/O pin | General-purpose I/O: LEDs (with series resistor), buttons (with pull-up) |
| MDC | MDCInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| INT_N | INT#/REFCLKOOutput pin | Logic output: drives the next input; do not tie outputs together |
| RST_N | RST#Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| TXEN | TXENInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| TXD0 | TXD0Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| TXD1 | TXD1Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| VDD2A | VDD2ASupply pin | Supply input: decouple with 100 nF close to the pin |
| LED2 | LED2/INTSEL#Output pin | Logic output: drives the next input; do not tie outputs together |
| LED1 | LED1/REGOFFOutput pin | Logic output: drives the next input; do not tie outputs together |
| VDDCR | VDDCRSupply pin | Supply input: decouple with 100 nF close to the pin |
| VDDIO | VDDIOSupply pin | Supply input: decouple with 100 nF close to the pin |
| VDD1A | VDD1ASupply pin | Supply input: decouple with 100 nF close to the pin |
| TXN | TXNAnalog pin | General-purpose I/O: LEDs (with series resistor), buttons (with pull-up) |
| TXP | TXPAnalog pin | General-purpose I/O: LEDs (with series resistor), buttons (with pull-up) |
| RXN | RXNAnalog pin | General-purpose I/O: LEDs (with series resistor), buttons (with pull-up) |
| RXP | RXPAnalog pin | General-purpose I/O: LEDs (with series resistor), buttons (with pull-up) |
| RBIAS | RBIASAnalog pin | General-purpose I/O: LEDs (with series resistor), buttons (with pull-up) |
| VSS | VSSGround pin | Ground |
PCB
Verified land pattern
VQFN-24-1EP_4x4mm_P0.5mm_EP2.5x2.5mm_ThermalVias| Package | Land pattern | Status | Source |
|---|---|---|---|
| VQFN-24 · LAN8720A-CP | VQFN-24-1EP_4x4mm_P0.5mm_EP2.5x2.5mm_ThermalVias | Verified land pattern | KiCad 10.0.7: symbol Interface_Ethernet:LAN8720A, footprint Package_DFN_QFN:VQFN-24-1EP_4x4mm_P0.5mm_EP2.5x2.5mm_ThermalVias |