Verilog (digital engine)74HC139v_hc139

74HC139 (2× 2:4 decoder)

74HC139 (2× 2:4 decoder): functional Verilog gate model, numbered SOIC pins as in the datasheet.

Schematic symbol

Key data

Category: Logic (Verilog)
Simulation model: Verilog (digital engine)
Manufacturer part number: 74HC139
Reference prefix: U
Pins: 16
Land pattern: SOIC-16_3.9x9.9mm_P1.27mm

Simulation model

The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.

Supply pins: 16 / 8
Top module: v_hc139
Output driver resistance: 50 Ω

Verilog source


module v_hc139(input nE1,nE2,input [1:0] A,B,output [3:0] nY,nZ);
assign nY=nE1?4'b1111:~(4'b0001<<A);
assign nZ=nE2?4'b1111:~(4'b0001<<B);
endmodule

Pins 16

Pin	Name	Use
1	nE1Input pin	Active-low control input: low = active; tie high when unused
2	A[0]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
3	A[1]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
4	nY[0]Output pin	Logic output: drives the next input; do not tie outputs together
5	nY[1]Output pin	Logic output: drives the next input; do not tie outputs together
6	nY[2]Output pin	Logic output: drives the next input; do not tie outputs together
7	nY[3]Output pin	Logic output: drives the next input; do not tie outputs together
8	GNDGround pin	Ground
9	nZ[3]Output pin	Logic output: drives the next input; do not tie outputs together
10	nZ[2]Output pin	Logic output: drives the next input; do not tie outputs together
11	nZ[1]Output pin	Logic output: drives the next input; do not tie outputs together
12	nZ[0]Output pin	Logic output: drives the next input; do not tie outputs together
13	B[1]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
14	B[0]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
15	nE2Input pin	Active-low control input: low = active; tie high when unused
16	VCCSupply pin	Supply input: decouple with 100 nF close to the pin

Parameters 1

Gate delaytpd

Default10n

PCB

Verified land patternSOIC-16_3.9x9.9mm_P1.27mm