Verilog (digital engine)74HC173v_hc173

74HC173 (4-bit register)

74HC173 (4-bit register): functional Verilog gate model, numbered SOIC pins as in the datasheet.

Schematic symbol

Key data

Category: Logic (Verilog)
Simulation model: Verilog (digital engine)
Manufacturer part number: 74HC173
Reference prefix: U
Pins: 16
Land pattern: SOIC-16_3.9x9.9mm_P1.27mm

Simulation model

The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.

Supply pins: 16 / 8
Top module: v_hc173
Output driver resistance: 50 Ω

Verilog source


module v_hc173(input CLK,MR,nE1,nE2,nOE1,nOE2,input [3:0] D,output [3:0] Q);
reg [3:0] q;
always @(posedge CLK or posedge MR) if(MR)q<=0;else if(!nE1 && !nE2)q<=D;
assign Q=(!nOE1 && !nOE2)?q:4'bzzzz;
endmodule

Pins 16

Pin	Name	Use
1	nOE1Input pin	Active-low control input: low = active; tie high when unused
2	nOE2Input pin	Active-low control input: low = active; tie high when unused
3	Q[0]Output pin	Logic output: drives the next input; do not tie outputs together
4	Q[1]Output pin	Logic output: drives the next input; do not tie outputs together
5	Q[2]Output pin	Logic output: drives the next input; do not tie outputs together
6	Q[3]Output pin	Logic output: drives the next input; do not tie outputs together
7	CLKInput pin	Logic input: never leave open (tie unused inputs to VCC or GND)
8	GNDGround pin	Ground
9	nE1Input pin	Active-low control input: low = active; tie high when unused
10	nE2Input pin	Active-low control input: low = active; tie high when unused
11	D[3]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
12	D[2]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
13	D[1]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
14	D[0]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
15	MRInput pin	Logic input: never leave open (tie unused inputs to VCC or GND)
16	VCCSupply pin	Supply input: decouple with 100 nF close to the pin

Parameters 1

Gate delaytpd

Default10n

PCB

Verified land patternSOIC-16_3.9x9.9mm_P1.27mm