Behavioural mixed-signal modelW25Q128JVPIQw25q128jv
W25Q128JV (16 MiB SPI flash)
Behavioral model: JEDEC ID EF 40 18, read 03/0B, page program, sector/block/chip erase with timing and BUSY, status register, power-down. Contents are kept during the run.
Key data
- Category
- ICs
- Simulation model
- Behavioural mixed-signal model
- Manufacturer part number
- W25Q128JVPIQ
- Reference prefix
- U
- Pins
- 8
- Land pattern
- WSON-8-1EP_6x5mm_P1.27mm
Simulation model
A behavioural model implements the interface of the chip (registers, protocol, timing) at its pins. The pins are connected to the analog circuit like CMOS pins.
- Model
- w25q128jv
- Supply pins
- 8 / 4
Pins 8
| Pin | Name | Use |
|---|---|---|
| 1 | /CSInput pin | Chip select, active low: pull-up 10 kΩ keeps the flash idle at reset |
| 6 | CLKInput pin | SPI clock |
| 5 | DIInput pin | Data in (MOSI) / IO0 |
| 2 | DOOutput pin | Data out (MISO) / IO1 |
| 3 | /WPInput pin | Write protect, active low: tie high (or IO2 in quad mode) |
| 7 | /HOLDInput pin | Hold, active low: tie high (or IO3 in quad mode) |
| 8 | VCCSupply pin | Supply 2.7–3.6 V: 100 nF to GND |
| 4 | GNDGround pin | Ground |
Parameters 1
Program/erase times
timingDefaulttyp
typmax
PCB
Verified land pattern
WSON-8-1EP_6x5mm_P1.27mm