Verilog (digital engine)74HC04v_hc04

74HC04 (6× inverter, numbered)

74HC04 (6× inverter, numbered): functional Verilog gate model, numbered SOIC pins as in the datasheet.

Schematic symbol

Key data

Category: Logic (Verilog)
Simulation model: Verilog (digital engine)
Manufacturer part number: 74HC04
Reference prefix: U
Pins: 14
Land pattern: SOIC-14_3.9x8.7mm_P1.27mm

Simulation model

The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.

Supply pins: 14 / 7
Top module: v_hc04
Output driver resistance: 50 Ω

Verilog source


module v_hc04(input [5:0] A,output [5:0] Y);assign Y=~A;endmodule

Pins 14

Pin	Name	Use
1	A[0]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
2	Y[0]Output pin	Logic output: drives the next input; do not tie outputs together
3	A[1]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
4	Y[1]Output pin	Logic output: drives the next input; do not tie outputs together
5	A[2]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
6	Y[2]Output pin	Logic output: drives the next input; do not tie outputs together
7	GNDGround pin	Ground
8	Y[3]Output pin	Logic output: drives the next input; do not tie outputs together
9	A[3]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
10	Y[4]Output pin	Logic output: drives the next input; do not tie outputs together
11	A[4]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
12	Y[5]Output pin	Logic output: drives the next input; do not tie outputs together
13	A[5]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
14	VCCSupply pin	Supply input: decouple with 100 nF close to the pin

Parameters 1

Gate delaytpd

Default10n

PCB

Verified land patternSOIC-14_3.9x8.7mm_P1.27mm