Verilog (digital engine)v_dff
D flip-flop
Positive-edge triggered, asynchronous reset (active low)
Key data
- Category
- Logic (Verilog)
- Simulation model
- Verilog (digital engine)
- Reference prefix
- U
- Pins
- 7
- Land pattern
- SOIC-8_3.9mm_P1.27mm
Simulation model
The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.
- Supply pins
- VCC / GND
- Output driver resistance
- 50 Ω
Verilog source
module dff(input D, CLK, nRST, output reg Q, output nQ);
always @(posedge CLK or negedge nRST)
if (!nRST) Q <= 1'b0;
else Q <= D;
assign nQ = ~Q;
endmodule
Pins 7
| Pin | Name | Use |
|---|---|---|
| D | DInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| CLK | CLKInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| nRST | nRSTInput pin | Active-low control input: low = active; tie high when unused |
| Q | QOutput pin | Logic output: drives the next input; do not tie outputs together |
| nQ | nQOutput pin | Logic output: drives the next input; do not tie outputs together |
| VCC | VCCSupply pin | Supply input: decouple with 100 nF close to the pin |
| GND | GNDGround pin | Ground |
Parameters 1
Gate delay
tpdDefault1n s
Delay per gate / clock→Q
PCB
Generic land pattern
SOIC-8_3.9mm_P1.27mmno known land pattern, generic SOIC-8_3.9mm_P1.27mm with pins in symbol order