Verilog (digital engine)AS6C62256-55SINv_as6c62256
AS6C62256 SRAM 32K×8
Static RAM 32K×8 (Alliance Memory, 2.7–5.5 V, 55 ns). Asynchronous read at CE̅ = OE̅ = low and WE̅ = high; write: data is latched on the rising edge of WE̅ or CE̅ (end of the write cycle), outputs high impedance during WE̅ = low. Contents after power-up 0 (real: random). Real package SOP-28 330 mil: check the footprint before manufacturing.
Key data
- Category
- Memory (Verilog)
- Simulation model
- Verilog (digital engine)
- Manufacturer part number
- AS6C62256-55SIN
- Reference prefix
- U
- Pins
- 28
- Land pattern
- SOIC-28W_7.5x17.9mm_P1.27mm
Simulation model
The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.
- Supply pins
- 28 / 14
- Top module
- v_as6c62256
Verilog source
module v_as6c62256(input [14:0] A,input nCE,nOE,nWE,inout [7:0] D);
reg [7:0] mem [0:32767];
// a write cycle ends when WE# or CE# rises (whichever first): data is taken there
wire nW=nCE|nWE;
always @(posedge nW) mem[A]<=D;
assign D=(!nCE && !nOE && nWE)?mem[A]:8'bzzzzzzzz;
endmodulePins 28
| Pin | Name | Use |
|---|---|---|
| 1 | A[14]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 2 | A[12]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 3 | A[7]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 4 | A[6]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 5 | A[5]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 6 | A[4]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 7 | A[3]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 8 | A[2]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 9 | A[1]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 10 | A[0]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 11 | D[0]I/O pin | Bidirectional data line (tri-state bus) |
| 12 | D[1]I/O pin | Bidirectional data line (tri-state bus) |
| 13 | D[2]I/O pin | Bidirectional data line (tri-state bus) |
| 14 | GNDGround pin | Ground |
| 15 | D[3]I/O pin | Bidirectional data line (tri-state bus) |
| 16 | D[4]I/O pin | Bidirectional data line (tri-state bus) |
| 17 | D[5]I/O pin | Bidirectional data line (tri-state bus) |
| 18 | D[6]I/O pin | Bidirectional data line (tri-state bus) |
| 19 | D[7]I/O pin | Bidirectional data line (tri-state bus) |
| 20 | nCEInput pin | Active-low control input: low = active; tie high when unused |
| 21 | A[10]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 22 | nOEInput pin | Active-low control input: low = active; tie high when unused |
| 23 | A[11]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 24 | A[9]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 25 | A[8]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 26 | A[13]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 27 | nWEInput pin | Active-low control input: low = active; tie high when unused |
| 28 | VCCSupply pin | Supply input: decouple with 100 nF close to the pin |
Parameters 1
Access time (model)
tpdDefault10n
PCB
Verified land pattern
SOIC-28W_7.5x17.9mm_P1.27mm