74HC595 (8-bit shift register, latched outputs)

Key data

Category

Logic (Verilog)

Simulation model

Verilog (digital engine)

Manufacturer part number

74HC595

Reference prefix

U

Pins

16

Land pattern

SOIC-16_3.9x9.9mm_P1.27mm

Notes

• Arduino: shiftOut(dataPin, clockPin, MSBFIRST, value) on SER and SRCLK, then a pulse on RCLK shows the byte on QA–QH (QH = first bit sent with MSBFIRST).
• Chain several chips: QH' to SER of the next one, SRCLK and RCLK in parallel.
• Tie SRCLR̅ to VCC and OE̅ to GND when you do not need them; each output drives an LED through its own resistor.

Simulation model

The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.

Supply pins

16 / 8

Top module

v_hc595

Output driver resistance

50 Ω

module v_hc595(input SER,SRCLK,RCLK,nSRCLR,nOE,output QA,QB,QC,QD,QE,QF,QG,QH,QHS);
reg [7:0] sr,st;
always @(posedge SRCLK or negedge nSRCLR) if(!nSRCLR)sr<=8'b0;else sr<={sr[6:0],SER};
always @(posedge RCLK) st<=sr;
assign {QH,QG,QF,QE,QD,QC,QB,QA}=nOE?8'bzzzzzzzz:st;
assign QHS=sr[7];
endmodule

Pins 16

Parameters 1

PCB