TL072 (dual JFET op-amp)

Key data

Category

ICs

Simulation model

SPICE subcircuit

Manufacturer part number

TL072CDR

Reference prefix

U

Pins

8

Land pattern

SOIC-8_3.9x4.9mm_P1.27mm

Notes

Two-stage macromodel per amplifier: the input stage saturates (slew rate), the gain stage has one dominant pole (gain-bandwidth product and open-loop gain from the datasheet), the output is clamped at the swing limits of the datasheet and has an output resistance. Input offset, bias currents, noise and the output current limit are not modelled.

• The bandwidth falls with the gain: a gain of 10 leaves about a tenth of the gain-bandwidth product. Large fast steps are limited by the slew rate.
• Needs about 1.5 V headroom to each rail; with a single supply, bias the inputs at half the supply.

Simulation model

The part is a small SPICE netlist (below), solved by the analog engine together with the rest of the circuit. Pin ids are the node names, {braces} are parameters.

E1m m1 4 8 4 0.5
R1in 3 2 1000000000000
E1a s1 m1 3 2 {2*PI*GBW*5/SR}
R1s s1 t1 1k
D1h t1 th1 DOPCL
V1h th1 m1 DC 4.965
D1l tl1 t1 DOPCL
V1l m1 tl1 DC 4.965
G1 m1 a1 t1 m1 {SR/5000000000}
R11 a1 m1 {AOL/((2*PI*GBW*5/SR)*(SR/5000000000))}
C11 a1 m1 1n
D1vh a1 hc1 DOPCL
V1vh 8 hc1 DC 1.095
D1vl lc1 a1 DOPCL
V1vl lc1 4 DC 1.095
E1o ob1 4 a1 4 1
R1o ob1 1 323
E2m m2 4 8 4 0.5
R2in 5 6 1000000000000
E2a s2 m2 5 6 {2*PI*GBW*5/SR}
R2s s2 t2 1k
D2h t2 th2 DOPCL
V2h th2 m2 DC 4.965
D2l tl2 t2 DOPCL
V2l m2 tl2 DC 4.965
G2 m2 a2 t2 m2 {SR/5000000000}
R21 a2 m2 {AOL/((2*PI*GBW*5/SR)*(SR/5000000000))}
C21 a2 m2 1n
D2vh a2 hc2 DOPCL
V2vh 8 hc2 DC 1.095
D2vl lc2 a2 DOPCL
V2vl lc2 4 DC 1.095
E2o ob2 4 a2 4 1
R2o ob2 7 323
RQ 8 4 1.071e+4

.model DOPCL D(IS=1e-15 N=0.05)

Pins 8

Parameters 3

PCB