Behavioural mixed-signal modelADS1291IRSMRads1291
ADS1291 (24-bit biopotential AFE)
Behavioral model after SBAS502C: SPI (CPOL 0, CPHA 1), registers, opcodes, RDATAC/RDATA, DRDY, 125 SPS–8 kSPS, PGA, test signal, input mux. Pins = pad numbers (RSM0032B).
Key data
- Category
- ICs
- Simulation model
- Behavioural mixed-signal model
- Manufacturer part number
- ADS1291IRSMR
- Reference prefix
- U
- Pins
- 33
- Land pattern
- TI_RSM0032B
Simulation model
A behavioural model implements the interface of the chip (registers, protocol, timing) at its pins. The pins are connected to the analog circuit like CMOS pins.
- Model
- ads1291
- Supply pins
- 23 / 24
Pins 33
| Pin | Name | Use |
|---|---|---|
| 3 | IN1NAnalog pin | Channel 1 negative input (electrode) |
| 4 | IN1PAnalog pin | Channel 1 positive input (electrode) |
| 5 | IN2NAnalog pin | Channel 2 negative input |
| 6 | IN2PAnalog pin | Channel 2 positive input |
| 31 | RESP_MODP/IN3PAnalog pin | Respiration modulation / channel 3 input |
| 32 | RESP_MODN/IN3NAnalog pin | Respiration modulation / channel 3 input |
| 28 | RLDINVAnalog pin | Right-leg drive inverting input |
| 29 | RLDIN/RLDREFAnalog pin | Right-leg drive input / reference |
| 30 | RLDOUTAnalog pin | Right-leg drive output: to the reference electrode |
| 1 | PGA1NAnalog pin | PGA output (for filtering or test) |
| 2 | PGA1PAnalog pin | PGA output (for filtering or test) |
| 7 | PGA2NAnalog pin | PGA output (for filtering or test) |
| 8 | PGA2PAnalog pin | PGA output (for filtering or test) |
| 18 | CSInput pin | SPI chip select (active low) |
| 20 | SCLKInput pin | SPI clock |
| 19 | DINInput pin | SPI data in (from MOSI) |
| 21 | DOUTOutput pin | SPI data out (to MISO) |
| 22 | DRDYOutput pin | Data ready (active low): to an interrupt pin |
| 15 | PWDN/RESETInput pin | Power-down / reset, active low: drive from a GPIO or tie high |
| 16 | STARTInput pin | START: high starts conversions (or use the START command) |
| 14 | CLKSELInput pin | Clock select: high = internal oscillator |
| 17 | CLKInput pin | Clock in/out |
| 26 | GPIO1/RCLK1Output pin | General-purpose I/O |
| 25 | GPIO2/RCLK2Output pin | General-purpose I/O |
| 9 | VREFPAnalog pin | Reference output: bypass capacitor to VREFN (value per datasheet) |
| 10 | VREFNAnalog pin | Reference negative: to AVSS |
| 11 | VCAP1Analog pin | Bypass capacitor to AVSS (value per datasheet) |
| 27 | VCAP2Analog pin | Bypass capacitor to AVSS (value per datasheet) |
| 12 | AVDDSupply pin | Analog supply: 1 µF + 100 nF to AVSS |
| 23 | DVDDSupply pin | Digital supply: 1 µF + 100 nF to DGND |
| 13 | AVSSGround pin | Analog ground |
| 33 | PADGround pin | Exposed pad: to AVSS |
| 24 | DGNDGround pin | Digital ground |
Parameters 3
Input noise
noiseDefaultoff
offdatasheet
SBAS502C tables 1–4 (3 V / 2.42 V)
Data frame
frameDefault72 bit
7248
Die temperature
tempDefault25 °C
PCB
Verified land pattern
TI_RSM0032B