Verilog (digital engine)v_pwm4
PWM generator (4-bit)
PWM with a period of 16 clocks; duty cycle = DUTY/16
Key data
- Category
- Logic (Verilog)
- Simulation model
- Verilog (digital engine)
- Reference prefix
- U
- Pins
- 9
- Land pattern
- SOIC-10_3.9mm_P1.27mm
Simulation model
The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.
- Supply pins
- VCC / GND
- Output driver resistance
- 50 Ω
Verilog source
module pwm4(input CLK, RST, input [3:0] DUTY, output PWM);
reg [3:0] cnt;
always @(posedge CLK or posedge RST)
if (RST) cnt <= 4'd0;
else cnt <= cnt + 4'd1;
assign PWM = cnt < DUTY;
endmodule
Pins 9
| Pin | Name | Use |
|---|---|---|
| CLK | CLKInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| RST | RSTInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| DUTY[0] | DUTY[0]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| DUTY[1] | DUTY[1]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| DUTY[2] | DUTY[2]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| DUTY[3] | DUTY[3]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| PWM | PWMOutput pin | Logic output: drives the next input; do not tie outputs together |
| VCC | VCCSupply pin | Supply input: decouple with 100 nF close to the pin |
| GND | GNDGround pin | Ground |
Parameters 1
Gate delay
tpdDefault1n s
Delay per gate / clock→Q
PCB
Generic land pattern
SOIC-10_3.9mm_P1.27mmno known land pattern, generic SOIC-10_3.9mm_P1.27mm with pins in symbol order