Verilog (digital engine)v_counter4
4-bit counter
Synchronous binary counter with enable, asynchronous reset (active high) and carry
Key data
- Category
- Logic (Verilog)
- Simulation model
- Verilog (digital engine)
- Reference prefix
- U
- Pins
- 10
- Land pattern
- SOIC-10_3.9mm_P1.27mm
Simulation model
The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.
- Supply pins
- VCC / GND
- Output driver resistance
- 50 Ω
Verilog source
module counter4(input CLK, RST, EN, output reg [3:0] Q, output CO);
always @(posedge CLK or posedge RST)
if (RST) Q <= 4'd0;
else if (EN) Q <= Q + 4'd1;
assign CO = EN & (Q == 4'hF);
endmodule
Pins 10
| Pin | Name | Use |
|---|---|---|
| CLK | CLKInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| RST | RSTInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| EN | ENInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| Q[0] | Q[0]Output pin | Logic output: drives the next input; do not tie outputs together |
| Q[1] | Q[1]Output pin | Logic output: drives the next input; do not tie outputs together |
| Q[2] | Q[2]Output pin | Logic output: drives the next input; do not tie outputs together |
| Q[3] | Q[3]Output pin | Logic output: drives the next input; do not tie outputs together |
| CO | COOutput pin | Logic output: drives the next input; do not tie outputs together |
| VCC | VCCSupply pin | Supply input: decouple with 100 nF close to the pin |
| GND | GNDGround pin | Ground |
Parameters 1
Gate delay
tpdDefault1n s
Delay per gate / clock→Q
PCB
Generic land pattern
SOIC-10_3.9mm_P1.27mmno known land pattern, generic SOIC-10_3.9mm_P1.27mm with pins in symbol order