Verilog (digital engine)74HC74v_hc74
74HC74 (2× D flip-flop)
74HC74 (2× D flip-flop): functional Verilog gate model, numbered SOIC pins as in the datasheet.
Key data
- Category
- Logic (Verilog)
- Simulation model
- Verilog (digital engine)
- Manufacturer part number
- 74HC74
- Reference prefix
- U
- Pins
- 14
- Land pattern
- SOIC-14_3.9x8.7mm_P1.27mm
Simulation model
The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.
- Supply pins
- 14 / 7
- Top module
- v_hc74
- Output driver resistance
- 50 Ω
Verilog source
module v_hc74(input [1:0] CLK,D,nCLR,nPRE,output [1:0] Q,nQ);
reg [1:0] q;
genvar i;generate for(i=0;i<2;i=i+1)begin:ff
always @(posedge CLK[i] or negedge nCLR[i] or negedge nPRE[i])
if(!nCLR[i])q[i]<=0;else if(!nPRE[i])q[i]<=1;else q[i]<=D[i];
end endgenerate
assign Q=q;assign nQ=~q;
endmodulePins 14
| Pin | Name | Use |
|---|---|---|
| 1 | nCLR[0]Input pin | Active-low control input: low = active; tie high when unused |
| 2 | D[0]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 3 | CLK[0]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 4 | nPRE[0]Input pin | Active-low control input: low = active; tie high when unused |
| 5 | Q[0]Output pin | Logic output: drives the next input; do not tie outputs together |
| 6 | nQ[0]Output pin | Logic output: drives the next input; do not tie outputs together |
| 7 | GNDGround pin | Ground |
| 8 | nQ[1]Output pin | Logic output: drives the next input; do not tie outputs together |
| 9 | Q[1]Output pin | Logic output: drives the next input; do not tie outputs together |
| 10 | nPRE[1]Input pin | Active-low control input: low = active; tie high when unused |
| 11 | CLK[1]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 12 | D[1]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 13 | nCLR[1]Input pin | Active-low control input: low = active; tie high when unused |
| 14 | VCCSupply pin | Supply input: decouple with 100 nF close to the pin |
Parameters 1
Gate delay
tpdDefault10n
PCB
Verified land pattern
SOIC-14_3.9x8.7mm_P1.27mm