Verilog (digital engine)AT28BV64B-20SUv_at28bv64b
AT28BV64B EEPROM (read model)
Real 8K×8 EEPROM type, 2.7–3.6 V; Verilog read model with CE/OE/WE and a programmed image saved with the circuit. Unused addresses = FF. WE is permanently high in this demo. Internal write cycles, page write and software protection are not simulated yet.
Key data
- Category
- Memory (Verilog)
- Simulation model
- Verilog (digital engine)
- Manufacturer part number
- AT28BV64B-20SU
- Reference prefix
- U
- Pins
- 28
- Land pattern
- SOIC-28W_7.5x17.9mm_P1.27mm
Simulation model
The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.
- Supply pins
- 28 / 14
- Top module
- v_at28bv64b
Verilog source
module v_at28bv64b(input [12:0] A,input nCE,nOE,nWE,output [7:0] D);
reg [7:0] value;
always @* begin value=8'hff;case(A)
endcase end
assign D=(!nCE && !nOE && nWE)?value:8'bzzzzzzzz;
endmodulePins 28
| Pin | Name | Use |
|---|---|---|
| 1 | NC1Passive pin | Not connected: leave open |
| 2 | A[12]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 3 | A[7]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 4 | A[6]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 5 | A[5]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 6 | A[4]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 7 | A[3]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 8 | A[2]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 9 | A[1]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 10 | A[0]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 11 | D[0]I/O pin | Bidirectional data line (tri-state bus) |
| 12 | D[1]I/O pin | Bidirectional data line (tri-state bus) |
| 13 | D[2]I/O pin | Bidirectional data line (tri-state bus) |
| 14 | GNDGround pin | Ground |
| 15 | D[3]I/O pin | Bidirectional data line (tri-state bus) |
| 16 | D[4]I/O pin | Bidirectional data line (tri-state bus) |
| 17 | D[5]I/O pin | Bidirectional data line (tri-state bus) |
| 18 | D[6]I/O pin | Bidirectional data line (tri-state bus) |
| 19 | D[7]I/O pin | Bidirectional data line (tri-state bus) |
| 20 | nCEInput pin | Active-low control input: low = active; tie high when unused |
| 21 | A[10]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 22 | nOEInput pin | Active-low control input: low = active; tie high when unused |
| 23 | A[11]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 24 | A[9]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 25 | A[8]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 26 | NC26Passive pin | Not connected: leave open |
| 27 | nWEInput pin | Active-low control input: low = active; tie high when unused |
| 28 | VCCSupply pin | Supply input: decouple with 100 nF close to the pin |
Parameters 1
Gate delay
tpdDefault10n
PCB
Verified land pattern
SOIC-28W_7.5x17.9mm_P1.27mm