Verilog (digital engine)74HC283v_hc283

74HC283 (4-bit full adder)

74HC283 (4-bit full adder): functional Verilog gate model, numbered SOIC pins as in the datasheet.

Schematic symbol

Key data

Category: Logic (Verilog)
Simulation model: Verilog (digital engine)
Manufacturer part number: 74HC283
Reference prefix: U
Pins: 16
Land pattern: SOIC-16_3.9x9.9mm_P1.27mm

Simulation model

The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.

Supply pins: 16 / 8
Top module: v_hc283
Output driver resistance: 50 Ω

Verilog source


module v_hc283(input [3:0] A,B,input CI,output [3:0] S,output CO);
assign {CO,S}={1'b0,A}+{1'b0,B}+CI;
endmodule

Pins 16

Pin	Name	Use
1	S[1]Output pin	Logic output: drives the next input; do not tie outputs together
2	B[1]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
3	A[1]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
4	S[0]Output pin	Logic output: drives the next input; do not tie outputs together
5	A[0]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
6	B[0]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
7	CIInput pin	Logic input: never leave open (tie unused inputs to VCC or GND)
8	GNDGround pin	Ground
9	COOutput pin	Logic output: drives the next input; do not tie outputs together
10	S[3]Output pin	Logic output: drives the next input; do not tie outputs together
11	B[3]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
12	A[3]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
13	S[2]Output pin	Logic output: drives the next input; do not tie outputs together
14	A[2]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
15	B[2]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
16	VCCSupply pin	Supply input: decouple with 100 nF close to the pin

Parameters 1

Gate delaytpd

Default10n

PCB

Verified land patternSOIC-16_3.9x9.9mm_P1.27mm