Hierarchical part (sub-schematic)74HC00hc00
74HC00 (MOSFET model)
Four NAND gates with 2 inputs each – teaching model of 16 discrete MOSFETs; not a Verilog IC model of the real HC process. For IC boards use the numbered models under "Logic (Verilog)".
Key data
- Category
- Logic (MOSFET models)
- Simulation model
- Hierarchical part (sub-schematic)
- Manufacturer part number
- 74HC00
- Reference prefix
- U
- Pins
- 14
- Land pattern
- SOIC-14_3.9x8.7mm_P1.27mm
Simulation model
The part is a sub-schematic of 30 parts. The simulation flattens it and simulates every part inside.
- Parts inside
- 30
Pins 14
| Pin | Name | Use |
|---|---|---|
| 1 | 1AInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 2 | 1BInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 3 | 1YOutput pin | Logic output: drives the next input; do not tie outputs together |
| 4 | 2AInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 5 | 2BInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 6 | 2YOutput pin | Logic output: drives the next input; do not tie outputs together |
| 7 | GNDGround pin | Ground |
| 8 | 3YOutput pin | Logic output: drives the next input; do not tie outputs together |
| 9 | 3AInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 10 | 3BInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 11 | 4YOutput pin | Logic output: drives the next input; do not tie outputs together |
| 12 | 4AInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 13 | 4BInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 14 | VCCSupply pin | Supply input: decouple with 100 nF close to the pin |
PCB
Verified land pattern
SOIC-14_3.9x8.7mm_P1.27mm