Verilog (digital engine)74HC161v_hc161

74HC161 (4-bit program counter)

74HC161 (4-bit program counter): functional Verilog gate model, numbered SOIC pins as in the datasheet.

Schematic symbol

Key data

Category: Logic (Verilog)
Simulation model: Verilog (digital engine)
Manufacturer part number: 74HC161
Reference prefix: U
Pins: 16
Land pattern: SOIC-16_3.9x9.9mm_P1.27mm

Simulation model

The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.

Supply pins: 16 / 8
Top module: v_hc161
Output driver resistance: 50 Ω

Verilog source


module v_hc161(input CLK,nCLR,nLOAD,ENP,ENT,input [3:0] D,output reg [3:0] Q,output RCO);
always @(posedge CLK or negedge nCLR)if(!nCLR)Q<=0;else if(!nLOAD)Q<=D;else if(ENP && ENT)Q<=Q+1'b1;
assign RCO=ENT && (&Q);
endmodule

Pins 16

Pin	Name	Use
1	nCLRInput pin	Active-low control input: low = active; tie high when unused
2	CLKInput pin	Logic input: never leave open (tie unused inputs to VCC or GND)
3	D[0]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
4	D[1]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
5	D[2]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
6	D[3]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
7	ENPInput pin	Logic input: never leave open (tie unused inputs to VCC or GND)
8	GNDGround pin	Ground
9	nLOADInput pin	Active-low control input: low = active; tie high when unused
10	ENTInput pin	Logic input: never leave open (tie unused inputs to VCC or GND)
11	Q[3]Output pin	Logic output: drives the next input; do not tie outputs together
12	Q[2]Output pin	Logic output: drives the next input; do not tie outputs together
13	Q[1]Output pin	Logic output: drives the next input; do not tie outputs together
14	Q[0]Output pin	Logic output: drives the next input; do not tie outputs together
15	RCOOutput pin	Logic output: drives the next input; do not tie outputs together
16	VCCSupply pin	Supply input: decouple with 100 nF close to the pin

Parameters 1

Gate delaytpd

Default10n

PCB

Verified land patternSOIC-16_3.9x9.9mm_P1.27mm