Hierarchical part (sub-schematic)74HC74hc74
74HC74 (MOSFET model)
Two D flip-flops, positive edge, with preset and clear (active low) – teaching model of 80 discrete MOSFETs; not a Verilog IC model of the real HC process. For IC boards use the numbered models under "Logic (Verilog)".
Key data
- Category
- Logic (MOSFET models)
- Simulation model
- Hierarchical part (sub-schematic)
- Manufacturer part number
- 74HC74
- Reference prefix
- U
- Pins
- 14
- Land pattern
- SOIC-14_3.9x8.7mm_P1.27mm
Simulation model
The part is a sub-schematic of 94 parts. The simulation flattens it and simulates every part inside.
- Parts inside
- 94
Pins 14
| Pin | Name | Use |
|---|---|---|
| 1 | 1CLRInput pin | Active-low control input: low = active; tie high when unused |
| 2 | 1DInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 3 | 1CLKInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 4 | 1PREInput pin | Active-low control input: low = active; tie high when unused |
| 5 | 1QOutput pin | Logic output: drives the next input; do not tie outputs together |
| 6 | 1Q̅Output pin | Logic output: drives the next input; do not tie outputs together |
| 7 | GNDGround pin | Ground |
| 8 | 2Q̅Output pin | Logic output: drives the next input; do not tie outputs together |
| 9 | 2QOutput pin | Logic output: drives the next input; do not tie outputs together |
| 10 | 2PREInput pin | Active-low control input: low = active; tie high when unused |
| 11 | 2CLKInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 12 | 2DInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 13 | 2CLRInput pin | Active-low control input: low = active; tie high when unused |
| 14 | VCCSupply pin | Supply input: decouple with 100 nF close to the pin |
PCB
Verified land pattern
SOIC-14_3.9x8.7mm_P1.27mm