Verilog (digital engine)74HC165v_hc165

74HC165 (8-bit parallel/serial)

74HC165 (8-bit parallel/serial): functional Verilog gate model, numbered SOIC pins as in the datasheet.

Schematic symbol

Key data

Category: Logic (Verilog)
Simulation model: Verilog (digital engine)
Manufacturer part number: 74HC165
Reference prefix: U
Pins: 16
Land pattern: SOIC-16_3.9x9.9mm_P1.27mm

Simulation model

The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.

Supply pins: 16 / 8
Top module: v_hc165
Output driver resistance: 50 Ω

Verilog source


module v_hc165(input CLK,INH,nLD,SER,input [7:0] D,output QH,nQH);
// Two transparent stages reproduce asynchronous parallel loading and the
// interchangeable clock/inhibit rising edges of the physical chip.
reg [7:0] master,slave;
wire ck=CLK|INH;
always @* if(!nLD)master=D;else if(!ck)master={slave[6:0],SER};
always @* if(!nLD)slave=D;else if(ck)slave=master;
assign QH=slave[7];assign nQH=~slave[7];
endmodule

Pins 16

Pin	Name	Use
1	nLDInput pin	Active-low control input: low = active; tie high when unused
2	CLKInput pin	Logic input: never leave open (tie unused inputs to VCC or GND)
3	D[4]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
4	D[5]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
5	D[6]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
6	D[7]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
7	nQHOutput pin	Logic output: drives the next input; do not tie outputs together
8	GNDGround pin	Ground
9	QHOutput pin	Logic output: drives the next input; do not tie outputs together
10	SERInput pin	Logic input: never leave open (tie unused inputs to VCC or GND)
11	D[0]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
12	D[1]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
13	D[2]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
14	D[3]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
15	INHInput pin	Logic input: never leave open (tie unused inputs to VCC or GND)
16	VCCSupply pin	Supply input: decouple with 100 nF close to the pin

Parameters 1

Gate delaytpd

Default10n

PCB

Verified land patternSOIC-16_3.9x9.9mm_P1.27mm