Verilog (digital engine)74HC157v_hc157
74HC157 (4× 2:1 multiplexer)
74HC157 (4× 2:1 multiplexer): functional Verilog gate model, numbered SOIC pins as in the datasheet.
Key data
- Category
- Logic (Verilog)
- Simulation model
- Verilog (digital engine)
- Manufacturer part number
- 74HC157
- Reference prefix
- U
- Pins
- 16
- Land pattern
- SOIC-16_3.9x9.9mm_P1.27mm
Simulation model
The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.
- Supply pins
- 16 / 8
- Top module
- v_hc157
- Output driver resistance
- 50 Ω
Verilog source
module v_hc157(input S,nE,input [3:0] A,B,output [3:0] Y);
assign Y=nE?4'b0:(S?B:A);
endmodulePins 16
| Pin | Name | Use |
|---|---|---|
| 1 | SInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 2 | A[0]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 3 | B[0]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 4 | Y[0]Output pin | Logic output: drives the next input; do not tie outputs together |
| 5 | A[1]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 6 | B[1]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 7 | Y[1]Output pin | Logic output: drives the next input; do not tie outputs together |
| 8 | GNDGround pin | Ground |
| 9 | Y[2]Output pin | Logic output: drives the next input; do not tie outputs together |
| 10 | B[2]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 11 | A[2]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 12 | Y[3]Output pin | Logic output: drives the next input; do not tie outputs together |
| 13 | B[3]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 14 | A[3]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 15 | nEInput pin | Active-low control input: low = active; tie high when unused |
| 16 | VCCSupply pin | Supply input: decouple with 100 nF close to the pin |
Parameters 1
Gate delay
tpdDefault10n
PCB
Verified land pattern
SOIC-16_3.9x9.9mm_P1.27mm