Verilog (digital engine)74LS182v_ls182

74LS182 (carry lookahead)

74LS182 (carry lookahead): functional Verilog gate model, numbered SOIC pins as in the datasheet.

Schematic symbol

Key data

Category: Logic (Verilog)
Simulation model: Verilog (digital engine)
Manufacturer part number: 74LS182
Reference prefix: U
Pins: 16
Land pattern: SOIC-16_3.9x9.9mm_P1.27mm

Simulation model

The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.

Supply pins: 16 / 8
Top module: v_ls182
Output driver resistance: 50 Ω

Verilog source


module v_ls182(input [3:0] nG,nP,input Cn,output Cnx,Cny,Cnz,nGo,nPo);
wire [3:0] g=~nG,p=~nP;
assign Cnx=g[0]|(p[0]&Cn);
assign Cny=g[1]|(p[1]&g[0])|(p[1]&p[0]&Cn);
assign Cnz=g[2]|(p[2]&g[1])|(p[2]&p[1]&g[0])|(p[2]&p[1]&p[0]&Cn);
assign nGo=~(g[3]|(p[3]&g[2])|(p[3]&p[2]&g[1])|(p[3]&p[2]&p[1]&g[0]));
assign nPo=~(&p);
endmodule

Pins 16

Pin	Name	Use
1	nG[1]Input pin	Active-low control input: low = active; tie high when unused
2	nP[1]Input pin	Active-low control input: low = active; tie high when unused
3	nG[0]Input pin	Active-low control input: low = active; tie high when unused
4	nP[0]Input pin	Active-low control input: low = active; tie high when unused
5	nG[3]Input pin	Active-low control input: low = active; tie high when unused
6	nP[3]Input pin	Active-low control input: low = active; tie high when unused
7	nPoOutput pin	Logic output: drives the next input; do not tie outputs together
8	GNDGround pin	Ground
9	CnzOutput pin	Logic output: drives the next input; do not tie outputs together
10	nGoOutput pin	Logic output: drives the next input; do not tie outputs together
11	CnyOutput pin	Logic output: drives the next input; do not tie outputs together
12	CnxOutput pin	Logic output: drives the next input; do not tie outputs together
13	CnInput pin	Logic input: never leave open (tie unused inputs to VCC or GND)
14	nG[2]Input pin	Active-low control input: low = active; tie high when unused
15	nP[2]Input pin	Active-low control input: low = active; tie high when unused
16	VCCSupply pin	Supply input: decouple with 100 nF close to the pin

Parameters 1

Gate delaytpd

Default10n

PCB

Verified land patternSOIC-16_3.9x9.9mm_P1.27mm