Verilog (digital engine)74HC154v_hc154

74HC154 (4:16 instruction decoder)

74HC154 (4:16 instruction decoder): functional Verilog gate model, numbered SOIC pins as in the datasheet.

Schematic symbol

Key data

Category: Logic (Verilog)
Simulation model: Verilog (digital engine)
Manufacturer part number: 74HC154
Reference prefix: U
Pins: 24
Land pattern: SOIC-24W_7.5x15.4mm_P1.27mm

Simulation model

The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.

Supply pins: 24 / 12
Top module: v_hc154
Output driver resistance: 50 Ω

Verilog source


module v_hc154(input [3:0] A,input nE1,nE2,output [15:0] nY);
assign nY=(nE1||nE2)?16'hffff:~(16'h0001<<A);
endmodule

Pins 24

Pin	Name	Use
1	nY[0]Output pin	Logic output: drives the next input; do not tie outputs together
2	nY[1]Output pin	Logic output: drives the next input; do not tie outputs together
3	nY[2]Output pin	Logic output: drives the next input; do not tie outputs together
4	nY[3]Output pin	Logic output: drives the next input; do not tie outputs together
5	nY[4]Output pin	Logic output: drives the next input; do not tie outputs together
6	nY[5]Output pin	Logic output: drives the next input; do not tie outputs together
7	nY[6]Output pin	Logic output: drives the next input; do not tie outputs together
8	nY[7]Output pin	Logic output: drives the next input; do not tie outputs together
9	nY[8]Output pin	Logic output: drives the next input; do not tie outputs together
10	nY[9]Output pin	Logic output: drives the next input; do not tie outputs together
11	nY[10]Output pin	Logic output: drives the next input; do not tie outputs together
12	GNDGround pin	Ground
13	nY[11]Output pin	Logic output: drives the next input; do not tie outputs together
14	nY[12]Output pin	Logic output: drives the next input; do not tie outputs together
15	nY[13]Output pin	Logic output: drives the next input; do not tie outputs together
16	nY[14]Output pin	Logic output: drives the next input; do not tie outputs together
17	nY[15]Output pin	Logic output: drives the next input; do not tie outputs together
18	nE1Input pin	Active-low control input: low = active; tie high when unused
19	nE2Input pin	Active-low control input: low = active; tie high when unused
20	A[3]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
21	A[2]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
22	A[1]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
23	A[0]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
24	VCCSupply pin	Supply input: decouple with 100 nF close to the pin

Parameters 1

Gate delaytpd

Default10n

PCB

Verified land patternSOIC-24W_7.5x15.4mm_P1.27mm