Verilog (digital engine)74HC670v_hc670
74HC670 (4×4-bit register file)
74HC670 (4×4-bit register file): functional Verilog gate model, numbered SOIC pins as in the datasheet.
Key data
- Category
- Logic (Verilog)
- Simulation model
- Verilog (digital engine)
- Manufacturer part number
- 74HC670
- Reference prefix
- U
- Pins
- 16
- Land pattern
- SOIC-16_3.9x9.9mm_P1.27mm
Simulation model
The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.
- Supply pins
- 16 / 8
- Top module
- v_hc670
- Output driver resistance
- 50 Ω
Verilog source
module v_hc670(input [1:0] RA,WA,input nWE,nRE,input [3:0] D,output [3:0] Q);
reg [3:0] words[0:3];
genvar i;generate for(i=0;i<4;i=i+1)begin:store
always @* if(!nWE && WA==i)words[i]=D;
end endgenerate
assign Q=nRE?4'bzzzz:words[RA];
endmodulePins 16
| Pin | Name | Use |
|---|---|---|
| 1 | D[1]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 2 | D[2]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 3 | D[3]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 4 | RA[1]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 5 | RA[0]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 6 | Q[3]Output pin | Logic output: drives the next input; do not tie outputs together |
| 7 | Q[2]Output pin | Logic output: drives the next input; do not tie outputs together |
| 8 | GNDGround pin | Ground |
| 9 | Q[1]Output pin | Logic output: drives the next input; do not tie outputs together |
| 10 | Q[0]Output pin | Logic output: drives the next input; do not tie outputs together |
| 11 | nREInput pin | Active-low control input: low = active; tie high when unused |
| 12 | nWEInput pin | Active-low control input: low = active; tie high when unused |
| 13 | WA[1]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 14 | WA[0]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 15 | D[0]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 16 | VCCSupply pin | Supply input: decouple with 100 nF close to the pin |
Parameters 1
Gate delay
tpdDefault10n
PCB
Verified land pattern
SOIC-16_3.9x9.9mm_P1.27mm