Behavioural mixed-signal modelSTPMIC1APQRstpmic1
STPMIC1A power management IC
PMIC for STM32MP1 boards: 4 buck converters (VOUT1–4, inductors from VLX to VOUT), 6 LDOs, DDR reference, boost and USB power switches, I²C control (address 0x33). STPMIC1A factory setting: with VIN ≥ 3.5 V it starts BUCK3 3.3 V (after 7 ms), BUCK1 1.2 V, BUCK4 3.3 V and LDO5 2.9 V (after 10 ms), LDO4 3.3 V (after 13 ms), then releases RSTn; BUCK2 (DDR, default 1.1 V) and the other LDOs are switched on by the firmware over I²C. RSTn, INTn: open drain. Boost, switches, watchdog and power-down by key are not modelled.
Key data
- Category
- Power
- Simulation model
- Behavioural mixed-signal model
- Manufacturer part number
- STPMIC1APQR
- Reference prefix
- U
- Pins
- 45
- Land pattern
- ST_WFQFN-44-1EP_5x6mm_P0.4mm_EP3.6x4.6mm
Simulation model
A behavioural model implements the interface of the chip (registers, protocol, timing) at its pins. The pins are connected to the analog circuit like CMOS pins.
- Model
- stpmic1
- Supply pins
- VIN / AGND
Pins 45
| Pin | Name | Use |
|---|---|---|
| VIN | VINSupply pin | Supply input: decouple with 100 nF close to the pin |
| BUCK1IN | BUCK1INSupply pin | Supply input: decouple with 100 nF close to the pin |
| BUCK2IN | BUCK2INSupply pin | Supply input: decouple with 100 nF close to the pin |
| BUCK3IN | BUCK3INSupply pin | Supply input: decouple with 100 nF close to the pin |
| BUCK4IN | BUCK4INSupply pin | Supply input: decouple with 100 nF close to the pin |
| LDO16IN | LDO16INSupply pin | Supply input: decouple with 100 nF close to the pin |
| LDO25IN | LDO25INSupply pin | Supply input: decouple with 100 nF close to the pin |
| LDO3IN | LDO3INSupply pin | Supply input: decouple with 100 nF close to the pin |
| SWIN | SWINSupply pin | Supply input: decouple with 100 nF close to the pin |
| VIO | VIOSupply pin | Supply input: decouple with 100 nF close to the pin |
| SCL | SCLInput pin | I²C clock: sensors, displays; pull-up (about 4.7 kΩ) to the supply |
| SDA | SDAI/O pin | I²C data: pull-up (about 4.7 kΩ) to the supply |
| INTn | INTnOutput pin | Logic output: drives the next input; do not tie outputs together |
| RSTn | RSTnI/O pin | General-purpose I/O: LEDs (with series resistor), buttons (with pull-up) |
| WAKEUP | WAKEUPInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| PONKEYn | PONKEYnInput pin · pulled up on the board | Logic input: never leave open (tie unused inputs to VCC or GND) |
| PWRCTRL | PWRCTRLInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| INTLDO | INTLDOOutput pin | Logic output: drives the next input; do not tie outputs together |
| VLX1 | VLX1Output pin | Logic output: drives the next input; do not tie outputs together |
| VOUT1 | VOUT1Supply pin | Supply input: decouple with 100 nF close to the pin |
| VLX2 | VLX2Output pin | Logic output: drives the next input; do not tie outputs together |
| VOUT2 | VOUT2Supply pin | Supply input: decouple with 100 nF close to the pin |
| VLX3 | VLX3Output pin | Logic output: drives the next input; do not tie outputs together |
| VOUT3 | VOUT3Supply pin | Supply input: decouple with 100 nF close to the pin |
| VLX4 | VLX4Output pin | Logic output: drives the next input; do not tie outputs together |
| VOUT4 | VOUT4Supply pin | Supply input: decouple with 100 nF close to the pin |
| LDO1OUT | LDO1OUTOutput pin | Logic output: drives the next input; do not tie outputs together |
| LDO2OUT | LDO2OUTOutput pin | Logic output: drives the next input; do not tie outputs together |
| LDO3OUT | LDO3OUTOutput pin | Logic output: drives the next input; do not tie outputs together |
| LDO4OUT | LDO4OUTOutput pin | Logic output: drives the next input; do not tie outputs together |
| LDO5OUT | LDO5OUTOutput pin | Logic output: drives the next input; do not tie outputs together |
| LDO6OUT | LDO6OUTOutput pin | Logic output: drives the next input; do not tie outputs together |
| VREFDDR | VREFDDROutput pin | Logic output: drives the next input; do not tie outputs together |
| VLXBST | VLXBSTInput pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| BSTOUT | BSTOUTOutput pin | Logic output: drives the next input; do not tie outputs together |
| VBUSOTG | VBUSOTGOutput pin | Logic output: drives the next input; do not tie outputs together |
| SWOUT | SWOUTOutput pin | Logic output: drives the next input; do not tie outputs together |
| PGND1 | PGND1Ground pin | Ground |
| PGND2 | PGND2Ground pin | Ground |
| PGND3 | PGND3Ground pin | Ground |
| PGND4 | PGND4Ground pin | Ground |
| PGND5 | PGND5Ground pin | Ground |
| GNDLDO | GNDLDOGround pin | Ground |
| AGND | AGNDGround pin | Ground |
| EPGND | EPGNDGround pin | Ground |
PCB
Verified land pattern
ST_WFQFN-44-1EP_5x6mm_P0.4mm_EP3.6x4.6mm| Package | Land pattern | Status | Source |
|---|---|---|---|
| WFQFN-44 · STPMIC1APQR | ST_WFQFN-44-1EP_5x6mm_P0.4mm_EP3.6x4.6mm | Verified land pattern | ST DS12792 Rev 10: table 3 pin description, figure 2 pin configuration, table 73 / figure 65 package and recommended footprint |