Verilog (digital engine)74HC151v_hc151

74HC151 (8:1 multiplexer)

74HC151 (8:1 multiplexer): functional Verilog gate model, numbered SOIC pins as in the datasheet.

Schematic symbol

Key data

Category: Logic (Verilog)
Simulation model: Verilog (digital engine)
Manufacturer part number: 74HC151
Reference prefix: U
Pins: 16
Land pattern: SOIC-16_3.9x9.9mm_P1.27mm

Simulation model

The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.

Supply pins: 16 / 8
Top module: v_hc151
Output driver resistance: 50 Ω

Verilog source


module v_hc151(input [7:0] D,input [2:0] S,input nG,output Y,nW);
assign Y=!nG && D[S];
assign nW=!Y;
endmodule

Pins 16

Pin	Name	Use
1	D[3]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
2	D[2]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
3	D[1]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
4	D[0]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
5	YOutput pin	Logic output: drives the next input; do not tie outputs together
6	nWOutput pin	Logic output: drives the next input; do not tie outputs together
7	nGInput pin	Active-low control input: low = active; tie high when unused
8	GNDGround pin	Ground
9	S[2]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
10	S[1]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
11	S[0]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
12	D[7]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
13	D[6]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
14	D[5]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
15	D[4]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
16	VCCSupply pin	Supply input: decouple with 100 nF close to the pin

Parameters 1

Gate delaytpd

Default10n

PCB

Verified land patternSOIC-16_3.9x9.9mm_P1.27mm