SPICE subcircuitNE555DRne555
NE555 (Timer)
Internal 5k/5k/5k divider (CTRL = ⅔ VCC), TRIG < ⅓ VCC sets, THR > ⅔ VCC resets, RESET < 0.7 V has priority; open-collector discharge. Astable: f ≈ 1.44 / ((R1 + 2 R2) · C). For CMOS (TLC555/LMC555) output drop 0 V.
Key data
- Category
- ICs
- Simulation model
- SPICE subcircuit
- Manufacturer part number
- NE555DR
- Reference prefix
- U
- Pins
- 8
- Land pattern
- SOIC-8_3.9x4.9mm_P1.27mm
Simulation model
The part is a small SPICE netlist (below), solved by the analog engine together with the rest of the circuit. Pin ids are the node names, {braces} are parameters.
SPICE netlist
R1 8 5 5k
R2 5 m 5k
R3 m 1 5k
U1 1 2 3 4 5 6 7 8 TIMER555 VDROP={VDROP}Pins 8
| Pin | Name | Use |
|---|---|---|
| 2 | TRIGInput pin | Trigger: below ⅓ VCC starts the output pulse |
| 6 | THRInput pin | Threshold: above ⅔ VCC ends the pulse |
| 5 | CTRLAnalog pin | Control voltage: 10 nF to GND when unused |
| 4 | RESETInput pin | Reset, active low: tie to VCC when unused |
| 3 | OUTOutput pin | Output (up to about 200 mA) |
| 7 | DISOutput pin | Discharge: open collector that empties the timing capacitor |
| 8 | VCCSupply pin | Supply 4.5–16 V: 100 nF to GND |
| 1 | GNDGround pin | Ground |
Parameters 1
Output drop high
VDROPDefault1.7 V
NE555 ≈ 1.7 V below VCC; CMOS 555 (TLC555) 0
PCB
Verified land pattern
SOIC-8_3.9x4.9mm_P1.27mm