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Built-in circuit elementnmos

N-MOSFET

N-channel MOSFET: 2N7002 (small signal) or AO3400A (logic-level power switch, 5.7 A).

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Schematic symbol

Key data

Category
Semiconductors
Simulation model
Built-in circuit element
Reference prefix
Q
Pins
3
Land pattern
SOT-23

Simulation model

Level-1 (Shichman-Hodges) MOSFET, body tied to source, constant gate capacitances. The type selects the SPICE model card.

Primitive
M
Model and limitations

Level-1 MOSFET channel model

Included effects

  • Cutoff, linear and saturation regions with channel-length modulation; reverse channel operation.
  • Constant gate-source and gate-drain capacitances when supplied by the model card.

Model limitations

  • No body diode, body effect, avalanche breakdown, subthreshold current or temperature dependence.
  • Gate charge and switching losses are not qualified by fixed capacitances. Device names do not establish manufacturer calibration.

Offline reference checks

  • 24 NMOS/PMOS DC bias points compared with ngspice Level 1.
  • Existing loaded NMOS/PMOS switch reference circuits.

DC comparison uses |VGS| = 0, 1, 1.8, 3.3 V and |VDS| = 0.1, 1, 3.3 V with stated reference parameters. Other conditions need additional validation.

Documented test coverage, not a live test result or manufacturer approval. Simulation results depend on the selected parameters and circuit.

Model cards

NMOS_2N7002 NMOS
VTO1.6
KP0.3
LAMBDA0.01
CGS2.2e-11
CGD3e-12
NMOS_AO3400A NMOS
VTO1.05
KP10
LAMBDA0.01
CGS6.3e-10
CGD7.5e-11

Pins 3

PinNameUse
DDPassive pinDrain: to the load (the load goes to the supply)
GGPassive pinGate: driven by a logic pin; 10–100 kΩ to GND keeps it off at reset
SSPassive pinSource: to GND (low-side switch)

Parameters 1

Typemodel
DefaultNMOS_2N7002
NMOS_2N7002NMOS_AO3400A

PCB

Verified land patternSOT-23