Verilog (digital engine)74HC00v_74hc00

74HC00 (4× NAND)

Four NAND gates with two inputs each

Schematic symbol

Key data

Category: Logic (Verilog)
Simulation model: Verilog (digital engine)
Manufacturer part number: 74HC00
Reference prefix: U
Pins: 14
Land pattern: SOIC-14_3.9x8.7mm_P1.27mm

Simulation model

The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.

Supply pins: VCC / GND
Output driver resistance: 50 Ω

Verilog source

module hc00(input A1, B1, A2, B2, A3, B3, A4, B4, output Y1, Y2, Y3, Y4);
  assign Y1 = ~(A1 & B1);
  assign Y2 = ~(A2 & B2);
  assign Y3 = ~(A3 & B3);
  assign Y4 = ~(A4 & B4);
endmodule

Pins 14

Pin	Name	Use
A1	A1Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
B1	B1Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
A2	A2Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
B2	B2Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
A3	A3Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
B3	B3Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
A4	A4Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
B4	B4Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
Y1	Y1Output pin	Logic output: drives the next input; do not tie outputs together
Y2	Y2Output pin	Logic output: drives the next input; do not tie outputs together
Y3	Y3Output pin	Logic output: drives the next input; do not tie outputs together
Y4	Y4Output pin	Logic output: drives the next input; do not tie outputs together
VCC	VCCSupply pin	Supply input: decouple with 100 nF close to the pin
GND	GNDGround pin	Ground

Parameters 1

Gate delaytpd

Default1n s

Delay per gate / clock→Q

PCB

Verified land patternSOIC-14_3.9x8.7mm_P1.27mm