Verilog (digital engine)74HC02v_hc02

74HC02 (4× NOR)

74HC02 (4× NOR): functional Verilog gate model, numbered SOIC pins as in the datasheet.

Schematic symbol

Key data

Category: Logic (Verilog)
Simulation model: Verilog (digital engine)
Manufacturer part number: 74HC02
Reference prefix: U
Pins: 14
Land pattern: SOIC-14_3.9x8.7mm_P1.27mm

Simulation model

The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.

Supply pins: 14 / 7
Top module: v_hc02
Output driver resistance: 50 Ω

Verilog source

module v_hc02(input [3:0] A,B,output [3:0] Y);assign Y=~(A|B);endmodule

Pins 14

Pin	Name	Use
1	Y[0]Output pin	Logic output: drives the next input; do not tie outputs together
2	A[0]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
3	B[0]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
4	Y[1]Output pin	Logic output: drives the next input; do not tie outputs together
5	A[1]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
6	B[1]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
7	GNDGround pin	Ground
8	A[2]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
9	B[2]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
10	Y[2]Output pin	Logic output: drives the next input; do not tie outputs together
11	A[3]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
12	B[3]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
13	Y[3]Output pin	Logic output: drives the next input; do not tie outputs together
14	VCCSupply pin	Supply input: decouple with 100 nF close to the pin

Parameters 1

Gate delaytpd

Default10n

PCB

Verified land patternSOIC-14_3.9x8.7mm_P1.27mm