Verilog (digital engine)74HC244v_hc244
74HC244 (8× tristate bus driver)
74HC244 (8× tristate bus driver): functional Verilog gate model, numbered SOIC pins as in the datasheet.
Key data
- Category
- Logic (Verilog)
- Simulation model
- Verilog (digital engine)
- Manufacturer part number
- 74HC244
- Reference prefix
- U
- Pins
- 20
- Land pattern
- SOIC-20W_7.5x12.8mm_P1.27mm
Simulation model
The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.
- Supply pins
- 20 / 10
- Top module
- v_hc244
- Output driver resistance
- 50 Ω
Verilog source
module v_hc244(input [1:0] nOE,input [7:0] A,output [7:0] Y);
assign Y[3:0]=nOE[0]?4'bzzzz:A[3:0];
assign Y[7:4]=nOE[1]?4'bzzzz:A[7:4];
endmodulePins 20
| Pin | Name | Use |
|---|---|---|
| 1 | nOE[0]Input pin | Active-low control input: low = active; tie high when unused |
| 2 | A[0]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 3 | Y[7]Output pin | Logic output: drives the next input; do not tie outputs together |
| 4 | A[1]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 5 | Y[6]Output pin | Logic output: drives the next input; do not tie outputs together |
| 6 | A[2]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 7 | Y[5]Output pin | Logic output: drives the next input; do not tie outputs together |
| 8 | A[3]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 9 | Y[4]Output pin | Logic output: drives the next input; do not tie outputs together |
| 10 | GNDGround pin | Ground |
| 11 | A[4]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 12 | Y[3]Output pin | Logic output: drives the next input; do not tie outputs together |
| 13 | A[5]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 14 | Y[2]Output pin | Logic output: drives the next input; do not tie outputs together |
| 15 | A[6]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 16 | Y[1]Output pin | Logic output: drives the next input; do not tie outputs together |
| 17 | A[7]Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| 18 | Y[0]Output pin | Logic output: drives the next input; do not tie outputs together |
| 19 | nOE[1]Input pin | Active-low control input: low = active; tie high when unused |
| 20 | VCCSupply pin | Supply input: decouple with 100 nF close to the pin |
Parameters 1
Gate delay
tpdDefault10n
PCB
Verified land pattern
SOIC-20W_7.5x12.8mm_P1.27mm