Key data
- Category
- Logic (Verilog)
- Simulation model
- Verilog (digital engine)
- Manufacturer part number
- 74HC04
- Reference prefix
- U
- Pins
- 14
- Land pattern
- SOIC-14_3.9x8.7mm_P1.27mm
Simulation model
The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.
- Supply pins
- VCC / GND
- Output driver resistance
- 50 Ω
Verilog source
module hc04(input A1, A2, A3, A4, A5, A6, output Y1, Y2, Y3, Y4, Y5, Y6);
assign {Y6, Y5, Y4, Y3, Y2, Y1} = ~{A6, A5, A4, A3, A2, A1};
endmodule
Pins 14
| Pin | Name | Use |
|---|---|---|
| A1 | A1Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| A2 | A2Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| A3 | A3Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| A4 | A4Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| A5 | A5Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| A6 | A6Input pin | Logic input: never leave open (tie unused inputs to VCC or GND) |
| Y1 | Y1Output pin | Logic output: drives the next input; do not tie outputs together |
| Y2 | Y2Output pin | Logic output: drives the next input; do not tie outputs together |
| Y3 | Y3Output pin | Logic output: drives the next input; do not tie outputs together |
| Y4 | Y4Output pin | Logic output: drives the next input; do not tie outputs together |
| Y5 | Y5Output pin | Logic output: drives the next input; do not tie outputs together |
| Y6 | Y6Output pin | Logic output: drives the next input; do not tie outputs together |
| VCC | VCCSupply pin | Supply input: decouple with 100 nF close to the pin |
| GND | GNDGround pin | Ground |
Parameters 1
Gate delay
tpdDefault1n s
Delay per gate / clock→Q
PCB
Verified land pattern
SOIC-14_3.9x8.7mm_P1.27mm