Verilog (digital engine)74LS181v_ls181

74LS181 (4-bit ALU)

74LS181 (4-bit ALU): functional Verilog gate model, numbered SOIC pins as in the datasheet.

Schematic symbol

Key data

Category: Logic (Verilog)
Simulation model: Verilog (digital engine)
Manufacturer part number: 74LS181
Reference prefix: U
Pins: 24
Land pattern: SOIC-24W_7.5x15.4mm_P1.27mm

Simulation model

The Verilog source is synthesized to gates with Yosys (WebAssembly) and simulated event by event. Outputs drive the analog circuit like CMOS pins through a driver resistance to the supply; inputs switch at 30 % and 70 % of the supply.

Supply pins: 24 / 12
Top module: v_ls181
Output driver resistance: 50 Ω

Verilog source


module v_ls181(input [3:0] A,B,S,input nCn,M,output [3:0] F,output AEQB,nP,nG,nCn4);
wire [3:0] P=A|(S[0]?B:4'b0000)|(S[1]?~B:4'b0000);
wire [3:0] G=(S[2]?(A&~B):4'b0000)|(S[3]?(A&B):4'b0000);
wire [4:0] sum={1'b0,P}+{1'b0,G}+{4'b0000,~nCn};
assign F=M?~(P^G):sum[3:0];
assign nCn4=~sum[4];
assign nG=~(G[3]|(P[3]&G[2])|(P[3]&P[2]&G[1])|(P[3]&P[2]&P[1]&G[0]));
assign nP=~(&P);
assign AEQB=(&F)?1'bz:1'b0;
endmodule

Pins 24

Pin	Name	Use
1	B[0]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
2	A[0]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
3	S[3]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
4	S[2]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
5	S[1]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
6	S[0]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
7	nCnInput pin	Active-low control input: low = active; tie high when unused
8	MInput pin	Logic input: never leave open (tie unused inputs to VCC or GND)
9	F[0]Output pin	Logic output: drives the next input; do not tie outputs together
10	F[1]Output pin	Logic output: drives the next input; do not tie outputs together
11	F[2]Output pin	Logic output: drives the next input; do not tie outputs together
12	GNDGround pin	Ground
13	F[3]Output pin	Logic output: drives the next input; do not tie outputs together
14	AEQBOutput pin	Logic output: drives the next input; do not tie outputs together
15	nPOutput pin	Logic output: drives the next input; do not tie outputs together
16	nCn4Output pin	Logic output: drives the next input; do not tie outputs together
17	nGOutput pin	Logic output: drives the next input; do not tie outputs together
18	B[3]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
19	A[3]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
20	B[2]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
21	A[2]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
22	B[1]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
23	A[1]Input pin	Logic input: never leave open (tie unused inputs to VCC or GND)
24	VCCSupply pin	Supply input: decouple with 100 nF close to the pin

Parameters 1

Gate delaytpd

Default10n

PCB

Verified land patternSOIC-24W_7.5x15.4mm_P1.27mm